1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, particularly, to a non-volatile semiconductor memory device having an erase gate for erasing data and a method of erasing data of the non-volatile semiconductor memory device.
2. Description of the Related Art
A non-volatile semiconductor memory device according to the present invention is a flash memory having a memory cell array composed of memory cells each having a control gate, a floating gate and an erase gate and arranged in a lattice formation as a basic construction and data stored in the memory cell array can be erased in the lump in memory blocks of a predetermined number of memory cells.
FIG. 1 is a block diagram showing a construction of a conventional non-volatile semiconductor memory device and FIG. 2 is a cross section of the non-volatile semiconductor memory device shown in FIG. 1. The non-volatile semiconductor memory device shown in FIGS. 1 and 2 is composed of a memory cell array 1 for storing data, a word decoder 2 for selecting the memory cells in column direction of the memory cell array 1, an erase gate decoder 3 for erasing data of the respective memory cells in the memory cell array and a booster circuit 4 for erasing the memory cell data by applying a voltage of 20V to the erase gate decoder 3. (For example Japanese-Laid Open No. hei2-292870 and Japanese-Laid Open No. hei2-110981) This type of a semiconductor memory device is called split gate type.
In FIG. 1, when data is to be written in a desired one of the memory cells of the memory cell array, a selection signal for selecting one of the memory cell columns which includes the desired memory cell is supplied from a word line WL of the word decoder 2 to control gates (CG) of the memory cells. The selection signal may be a positive voltage having a relatively large absolute value, for example, 12V. Thereafter, a desired bit line BL is selected and a positive voltage having a relatively large absolute value, for example, 7V, is applied to a drain D of the desired memory cell through the selected bit line BL. Assuming, in this case, that a P type semiconductor substrate P-SUB 10 and sources S of the memory cells are ground potential, electron is injected from the side of the drain D of a channel portion of the semiconductor substrate P-SUB 10 to the floating gate FG of the memory cells by the channel hot electron, causing a threshold voltage of the memory cell to be increased. Thus, data is written in the selected memory cell.
On the other hand, when data of a desired memory cell is to be read, a selection signal which may be, for example, 5V for selecting one of the memory cell columns which includes the desired memory cell is supplied from a word line WL of the word decoder 2 to control gates (CG) of the memory cells. In this case, a positive voltage having a relatively small absolute value, for example, 1.5V is applied to drains D of the memory cells and the source S of the desired memory cell is made ground potential. The desired memory cell being erased becomes selectively turned on and a predetermined read current flows therethrough. A logical level of the stored data is determined by detecting the read current.
In a case where data in memory cells are to be erased, a voltage of 20V is applied from the erase gate decoder 3 to an erase line EL. Thus, data of all memory cells having the erase gates EG connected to the erase line EL are erased. That is, when the high voltage of 20V is applied to the erase line EL, the erase gates EG of the memory cells connected to the erase line EL become 20V. Assuming, in this case, that the sources S and the drains D of these memory cells are ground potential, electrons of the floating gates FG 13 of the memory cells are pulled toward the side of the erase gates EG by F-N tunnel phenomenon as shown by arrows in FIG. 2. As a result, data of these memory cells are erased. In this case, since an insulating film between the control gate CG and the erase gate is designed thick enough, there is no electron pull-in phenomenon occurs from the control gate to the erase gate.
Incidentally, reference numerals 11 in FIG. 2 depicts an insulating film of SiO.sub.2, 12 and 14 insulating films, 13 the floating gate, 15 the control gate and 16 the erase gate.
As mentioned, in order to erase data of the memory cells, a voltage as high as about 20V is required. Since, in the conventional semiconductor memory device, the erase voltage is generated by the booster circuit, power consumption in the booster circuit is large and a control circuit such as the erase gate decoder for supplying the high erase voltage to the memory cells must have a structure withstanding such high voltage. In order to solve the problem of, for example, the necessity of high voltage withstanding structure of the control circuit, the thickness of the gate oxide film must be made thick enough, causing miniaturization of the semiconductor memory device to be difficult.